1. Field of the Invention
The present invention relates generally to semiconductor memory devices and manufacturing methods thereof, and more specifically, to a memory structure for SRAM (Static Random Access Memory) and a manufacturing method thereof.
2. Description of the Background Art
Conventionally, SRAM is known as one kind of semiconductor memory device. FIG. 42 is an equivalent circuit diagram showing one memory cell of a conventional SRAM. Referring to FIG. 42, the memory cell uses a p type MOS (Metal Oxide Semiconductor) as a load, and is formed of six transistors. More specifically, a pair of driver transistors (for driving) Q.sub.1 and Q.sub.2 (n type MOS transistors) and a pair of load transistors Q.sub.5 and Q.sub.6 (p type MOS transistors) are connected with each other to constitute a flip-flop circuit.
The source regions 110 and 111 of the pair of load transistors Q.sub.5 and Q.sub.6 are connected to a power supply V.sub.cc. The source regions of driver transistors Q.sub.1 and Q.sub.2 are connected to GNDs 112 and 113.
A pair of access transistors Q.sub.3 and Q.sub.4 (n type MOS transistors) are connected to storage nodes 114 and 115, respectively. A bit line 107 is connected to one of the source/drain regions of access transistor Q.sub.3. A bit line 108 is connected to one of the source/drain regions of access transistor Q.sub.4. The gate electrodes of access transistors Q.sub.3 and Q.sub.4 are connected to a word line 109.
Now, a conventional SRAM memory cell structure will be described by way of illustrating a document (International Electron Device Meeting 1991 Technical Digest pp. 481-484).
FIGS. 43A and 43B are plan views showing a conventional SRAM memory cell structure divided into two stages from the bottom layer. More specifically, FIG. 43A illustrates driver transistors Q1 and Q2 and access transistors Q.sub.3 and Q.sub.4 formed on a substrate, while FIG. 43B illustrates thin film transistors (TFT) Q.sub.5 and Q.sub.6. FIG. 44 is a schematic sectional view taken along line G--G in FIGS. 43A and 43B.
Referring to FIGS. 43A, 43B, and 44, in the conventional memory cell, a pair of driver transistors Q.sub.1 and Q.sub.2 and a pair of access transistor Q.sub.3 and Q.sub.4 are formed at a main surface of a p type well 120. Driver transistor Q.sub.1 has a drain region 125a and a source region 125b opposing to each other with a channel region 125c therebetween, and a gate electrode 124. Driver transistor Q.sub.2 has a drain region 126a and a source region 126b opposing to each other with a channel region 126c therebetween, and a gate electrode 123.
Access transistor Q.sub.3 has a pair of source/drain regions 125d opposing to each other with a channel region 125e therebetween, and a gate electrode 121. Access transistor Q.sub.4 has a pair of source/drain regions 126d opposing to each other with a channel region 126e therebetween, and a gate electrode 122.
These transistors are formed of n type MOS transistors having source/drain regions formed on the main surface of p type well 120. The gate electrode 123 of driver transistor Q.sub.2 is connected to the source/drain region 125d of access transistor Q.sub.3 and the drain region 125a of driver transistor Q.sub.1 through a contact portion 123a. The gate electrode 124 of driver transistor Q.sub.1 is connected to the source/drain region 126d of access transistor Q.sub.4 and the drain region 126a of driver transistor Q.sub.2 through a contact portion 124a.
The drain region 143a of load transistor Q.sub.5 and the gate electrode 142 of load transistor Q.sub.6 are connected to the gate electrode 124 of driver transistor Q.sub.1 through a contact portion 143d. The drain region 144a of load transistor Q.sub.6 and the gate electrode 141 of load transistor Q.sub.5 are connected to the gate electrode 123 of driver transistor Q.sub.2 through a contact portion 144d.
A tungsten silicide layer 135 to be a GND line is formed at the position of an intermediate layer between driver transistor Q.sub.1, Q.sub.2 and access transistor Q.sub.3, Q.sub.4, and load transistors Q.sub.5, Q.sub.6.
A bit line 139 is connected to the source/drain region 125d of access transistor Q.sub.3 with a plug layer 137 therebetween. The other bit line (not shown) is connected to the source/drain region 126d of access transistor Q.sub.4 with a plug layer therebetween as in the case of bit line 139.
Load transistors Q.sub.5 and Q.sub.6 each formed of a thin film transistor have gate electrodes 141 and 142 lying under channel regions 143c and 144c, respectively, and each constitutes a so-called bottom gate type transistor.
FIG. 45 is a sectional view showing a typical cross section of a thin film transistor used for load transistors Q.sub.5 and Q.sub.6. Referring to FIG. 45, the thin film transistor includes channel region 144c, drain region 144a, and source region 144b formed in a semiconductor layer such as of polycrystalline silicon. Gate electrode 142 is formed at a position opposing to channel region 144c with an insulating layer therebetween. FIG. 46 is a graphic representation showing the current characteristic of the above-described thin film transistor. In FIG. 46, Vd represents drain voltage, Vg gate voltage, and Id drain current.
In such an SRAM, in order to increase the integration density of memory cells, an area occupied by each memory cell on plane must be reduced. More specifically, the area on plane occupied by driver transistors Q.sub.1, Q.sub.2, access transistors Q.sub.3, Q.sub.4, and load transistors Q.sub.5, Q.sub.6 must be reduced. The above-described conventional memory cell is however encountered with the following two disadvantages in increasing integration density.
The first disadvantage is instability in operation at the time of reading. Now, this disadvantage will be described in more detail.
FIGS. 47A and 47B are diagrams showing an equivalent circuit of the memory cell shown in FIG. 42 by dividing it into two inverter circuits related to reading operation. Referring to FIGS. 47A and 47B, load transistors Q.sub.5 and Q.sub.6 are not illustrated, because current flowing across them is significantly small. The reading characteristic of the memory cell is produced from voltage change at the storage node thereof, with a bit line and a word line fixed to Vcc, while changing the gate voltage of a driver transistor (voltage at the storage node of the other side).
FIG. 48 is a graphic representation showing the reading characteristic of the above-described SRAM. Referring to FIG. 48, the abscissa represents the voltage of storage node 115, while the ordinate represents the voltage of storage node 114. Curve .alpha..sub.1 represents the voltage change characteristic of storage node 114 when the voltage of storage node 115 is changed. Curve .gamma..sub.1 represents the voltage change characteristic of storage node 115 when the voltage of storage node 114 is changed. Curves .alpha..sub.1 and .gamma..sub.1 cross at three points P.sub.1, P.sub.2, and P.sub.3. Point P.sub.3 corresponds to storage node 114 storing "High" data, while point P.sub.1 corresponds to storage node 115 storing "High" data. Point P.sub.2 is an unstable point, and voltage does not stop at point P.sub.2 at the time of reading. In the Figure, a region defined by circle h.sub.1 is a so-called "memory cell eye". Generally, the larger the memory cell eye is, the more stable will be the reading operation.
The memory cell eye is discussed in Evert Seevinck et al., IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. SC-22, No. 5, Oct. 1987 pp. 748-754, and H. Shinohara et al., VLSI '82, pp. 106-107.
There are several ways of enlarging a memory cell eye, and two approaches will be described in the following. The first method is to enlarge the driving capability ratio .beta. of driver transistor and access transistor (in other words driving capability of driver transistor/driving capability of access transistor). FIG. 49 is a graphic representation showing the reading characteristic when the driving capability ratio .beta. is increased with respect to the case shown in FIG. 48. Referring to FIG. 49, the memory cell eye is enlarged from circle h.sub.1 to circle h.sub.2.
The second approach is to reduce threshold voltage V.sub.th of access transistor. Vcc-.theta..sub.1 (distance between Vcc and .theta..sub.1) and Vcc-.theta..sub.2 (distance between Vcc and .theta..sub.2) in FIG. 48 correspond to the threshold voltages V.sub.th of access transistors Q.sub.3 and Q.sub.4, respectively. It is noted that .theta..sub.1 and .theta..sub.2 are High level voltages of the outputs of the respective inverters. FIG. 50 is a graphic representation showing the characteristic when the threshold voltage V.sub.th of access transistor is reduced with respect to the case of FIG. 48. Referring to FIG. 50, if the threshold voltages V.sub.th of access transistors Q.sub.3 and Q.sub.4 are reduced to Vcc-.theta..sub.3 and Vcc-.theta..sub.4, respectively, the memory cell eye is enlarged from circle h.sub.1 to circle h.sub.3.
Referring to FIG. 43A, a conventional approach for enlarging a memory cell eye is to increase the gate widths W.sub.D of driver transistors Q.sub.1 and Q.sub.2, or to reduce the gate widths W.sub.A of access transistors Q.sub.3 and Q.sub.4. This is because the driving capability of a transistor is substantially proportional to its gate width. To increase the gate width W.sub.D of a driver transistor however hinders the memory cell from being reduced in size, and therefore is not preferable in view of high intensity integration. Meanwhile, to reduce the gate width W.sub.A of an access transistor gives rise to increase in the threshold voltage V.sub.th of the access transistor due to the narrow channel effect. Therefore, the memory cell eye is reduced conversely as described above, resulting in unstable reading operation.
As described above, such a conventional SRAM memory cell structure can not provide increase in integration density while maintaining operation stability.
The second disadvantage is due to the limits of manufacture by photolithography techniques. Now, the limits will be described in more detail.
Load transistors Q.sub.5 and Q.sub.6 employed in the conventional SRAM memory cell structure shown in FIGS. 43A and 43B are both bottom gate type thin film transistors. Referring to FIG. 43B in particular, the gates 141 and 142 of load transistors Q.sub.5 and Q.sub.6 are formed of one layer. More specifically, when load transistors Q.sub.5 and Q.sub.6 are formed, a conductive layer is formed first, and then gate electrodes 141 and 142 are formed from the conductive layer by patterning utilizing a photolithography technique or the like. In the present state of the art, a minimum manufacturing size in patterning by means of photolithography is about 0.35 .mu.m and therefore the size of each portion of gate electrodes 141 and 142 patterned by means of photolithography (L.sub.3 and L.sub.4, for example) can not be smaller than 0.35 .mu.m.
The source/drain regions of load transistor Q.sub.5, Q.sub.6 and layers 143, 144 to be channel regions are both also formed of one layer. Accordingly, the size of each portion of layers 143 and 144 (L.sub.5 for example) can not be smaller than 0.35 .mu.m either.
As described above, with the limits in the manufacture utilizing photolithography techniques, it is difficult to reduce the occupied area of load transistors Q.sub.5 and Q.sub.6 on plane, and the conventional SRAM memory cell structure is not statable for high density integration in this regard as well.
The structure of load transistors Q.sub.5, Q.sub.6 which is less susceptible to the limits in the manufacture by photolithography techniques as described above is disclosed in Japanese Patent Laying-Open No. 3-34569.
Meanwhile, FIG. 51 is a plan view schematically showing the structure of a load transistor in Japanese Patent Laying-Open No. 3-34569. Referring to FIG. 51, the pair of load transistors are formed of two polycrystalline silicon layers 301 and 303 piled upon each other with an insulating film (not shown) therebetween. A drain region 301a and a source region 301b are formed with a channel region 301c therebetween in polycrystalline silicon layer 301. A drain region 303a and a source region 303b are formed with a channel region 303c therebetween in polycrystalline silicon layer 303. A drain region 303a to be a gate electrode is present on the underlying channel region 301c with an insulating film therebetween. Drain region 301a to be a gate electrode is present under the overlying channel region 303c with the insulating film therebetween.
Thus, in the structure of the pair of load transistors, one constitutes a bottom gate type transistor and the other a top gate type transistor. The drain region of one transistor uses the gate electrode of the other transistor. Therefore, the limits in the manufacture by photolithography described above are reduced. The load transistor structure is therefore suitable for high density integration. The drain region 301a of the underlying polycrystalline silicon film 301 is not covered with overlying polycrystalline silicon film 303. Accordingly, an impurity can be implanted into drain region 301a in a self-aligned manner.
In the load transistor structure, however, channel regions 301c and 303c both has an approximately L-shape. If, for example, misregistration of a mask at the time of patterning polycrystalline silicon thin film 303 causes the overlying polycrystalline silicon thin film 303 to be shifted with respect to the underlying polycrystalline silicon thin film 301 in the direction indicated by arrow J or K, the sizes L.sub.6, L.sub.7, W.sub.1, and W.sub.2 of the portions of channel regions 301c and 303c can easily be changed.
FIG. 52 is a plan view schematically showing how the dimension of a channel region is changed by misregistration of a mask. Referring to FIG. 52, the load transistor pair structure shown in FIG. 51 has its channel region dimension easily changed. Accordingly, a load transistor having a desired characteristic can not be obtained. It is also difficult to provide stable operation.
As described above, in load transistors employed for a conventional SRAM memory cell structure, it was not possible to provide a structure suitable for high intensity integration while maintaining stable operation.